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DRAM
Austin Semiconductor, Inc. 1 MEG x 4 DRAM
Fast Page Mode DRAM
AVAILABLE AS MILITARY SPECIFICATIONS
* SMD 5962-90847 * MIL-STD-883
DQ1 DQ2 WE\ RAS\ A9 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 10
20-Pin DIP (C, CN)
MT4C4001J
PIN ASSIGNMENT (Top View)
20 19 18 17 16 15 14 13 12 11 Vss DQ4 DQ3 CAS\ OE\ A8 A7 A6 A5 A4
20-Pin SOJ (ECJ), 20-Pin LCC (ECN), & 20-Pin Gull Wing (ECG)
DQ1 DQ2 WE\ RAS\ A9 1 2 3 4 5 26 25 24 23 22 Vss DQ4 DQ3 CAS\ OE\
FEATURES
* Industry standard x4 pinout, timing, functions, and packages * High-performance, CMOS silicon-gate process * Single +5V10% power supply * Low-power, 2.5mW standby; 300mW active, typical * All inputs, outputs, and clocks are fully TTL and CMOS compatible * 1,024-cycle refresh distributed across 16ms * Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR), and HIDDEN * FAST PAGE MODE access cycle * CBR with WE\ a HIGH (JEDEC test mode capable via WCBR)
A0 A1 A2 A3 Vcc
9 10 11 12 13
18 17 16 15 14
A8 A7 A6 A5 A4
20-Pin DIP (CZ) OE\ 1 DQ3 3 Vss 5 2 CAS\ 4 DQ4 6 DQ1 8 WE\ 10 A9 12 A1 14 A3 16 A4 18 A6 20 A8
DQ2 7 RAS\ 9
A0 11 A2 13 Vcc 15 A5 17 A7 19
OPTIONS
* Timing 70ns access 80ns access 100ns access 120ns access * Packages Ceramic DIP (300 mil) Ceramic DIP (400 mil) Ceramic LCC* Ceramic ZIP Ceramic SOJ Ceramic Gull Wing
MARKING
-7 -8 -10 -12
GENERAL DESCRIPTION
The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS\ is used to latch the first 10 bits and CAS\ the later 10 bits. A READ or WRITE cycle is selected with the WE\ input. A logic HIGH on WE\ dictates READ mode while a logic LOW on WE\ dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE\ or CAS\, whichever occurs last. If WE\ goes LOW prior to CAS\ going LOW, the output pin(s) remain open (High-Z) until the next CAS\ cycle. If WE\ goes LOW after data reaches the output pin(s), Qs are activated and retain the selected cell data as long as CAS\ remains low (regardless of WE\ or RAS\). This LATE WE\ pulse results in a READ-WRITE cycle. The four data inputs and four data outputs are routed through four pins using common I/O and pin direction is controlled by WE\ and OE\. FAST-PAGEMODE operations allow faster data operations (READ, WRITE, or READ-MODIFY-WRITE) within a row address (A0-A9) defined page boundary. The FAST PAGE MODE (continued)
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
CN C ECN CZ ECJ ECG
No. No. No. No. No. No.
103 104 202 400 504 600
*NOTE: If solder-dip and lead-attach is desired on LCC packages, lead-attach must be done prior to the solderdip operation.
For more products and information please visit our web site at www.austinsemiconductor.com
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION (cont.)
cycle is always initiated with a row address strobe-in by RAS\ followed by a column address strobed-in by CAS\. CAS\ may be toggled-in by holding RAS\ LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS\ HIGH terminates the FAST PAGE MODE operation. Returning RAS\ and CAS\ HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS\ HIGH time. Memory cell data is retained in its corrected stated by maintaining power and executing any RAS\ cycle (READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or HIDDEN REFRESH) so that all 1,024 combinations of RAS\ addresses (A0-A9) are executed at least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS\ addressing.
MT4C4001J
FUNCTIONAL BLOCK DIAGRAM
FAST PAGE MODE
WE\ CAS\
*EARLY-WRITE DETECTION CIRCUIT
DATA IN BUFFER
DATA OUT BUFFER
4
4 4
DQ1 DQ2 DQ3 DQ4
NO. 2 CLOCK GENERATOR OE\
10
10 10
ROW DECODER
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
COLUMN ADDRESS BUFFER
REFRESH CONTROLLER
10
COLUMN DECODER
1024
4
Vcc Vss
SENSE AMPLIFIERS I/O GATING
1024 x 4
REFRESH COUNTER MEMORY ARRAY
ROW ADDRESS BUFFERS (10)
1024
10
RAS\
NO. 1 CLOCK GENERATOR
NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE) CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc. TRUTH TABLE
ADDRESSES FUNCTION Standby READ EARLY-WRITE READ-WRITE FAST-PAGE-MODE 1st Cycle READ 2nd Cycle FAST-PAGE-MODE 1st Cycle EARLY-WRITE 2nd Cycle FAST-PAGE-MODE 1st Cycle READ-WRITE 2nd Cycle RAS\-ONLY REFRESH READ HIDDEN REFRESH WRITE CAS\-BEFORE-RAS\ REFRESH RAS\ H L L L L L L L L L L LHL LHL HL CAS\ HX L L L HL HL HL HL HL HL H L L L WE\ X H L HL H H L L HL HL X H L H OE\ X L X LH L L X X LH LH X L X X R X ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW ROW ROW X
t
MT4C4001J
DATA IN/OUT DQ1-DQ4 High-Z Data Out Data In Data Out/Data In Data Out Data Out Data In Data In Data Out/Data In Data Out/Data In High-Z Data Out Data In High-Z
C X COL COL COL COL COL COL COL COL COL n/a COL COL X
t
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Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Vss.................-1.0V to +7.0V Storage Temperature.......................................-65oC to +150oC Power Dissipation.................................................................1W Short Circuit Output Current...........................................50mA Lead Temperature (soldering 5 seconds).....................+270oC
MT4C4001J
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS (NOTES: 1, 3, 4, 6, 7) (-55C < TA < 125C; VCC = 5V 10%)
PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, All Inputs Input Low (Logic 0) Voltage, All Inputs INPUT LEAKAGE CURRENT Any Input 0V < VIN < 5.5V Vcc = 5.5V (All other pints not under test = 0V) OUTPUT LEAKAGE CURRENT (Q is Disabled, 0V < VOUT < 5.5V) Vcc = 5.5V OUTPUT LEVELS Output High Voltage (IOUT = -5mA) Output Low Voltage (IOUT = 4.2mA) SYM VCC VIH VIL II MIN 4.5 2.4 -0.5 -5 MAX 5.5 VCC+0.5 0.8 5 UNITS V V V A NOTES
IOZ VOH VOL
-5 2.4
5
A V
0.4
MAX -10 4 2
V
PARAMETER/CONDITION STANDBY CURRENT (TTL) (RAS\ = CAS\ = VIH) STANDBY CURRENT (CMOS) (RAS\ = CAS\ = VCC -0.2V; all other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average Power-Supply Current (RAS\, CAS\, Address Cycling: tRC = tRC(MIN)) OPERATING CURRENT: FAST PAGE MODE Average Power-Supply Current (RAS\ = VIL, CAS\, Address Cycling: tPC = tPC (MIN)) REFRESH CURRENT: RAS\-ONLY Average Power-Supply Current (RAS\ Cycling, CAS\ = VIH: tRC = tRC (MIN)) REFRESH CURRENT: CAS\-BEFORE-RAS\ Average Power-Supply Current (RAS\, CAS\, Address Cycling: tRC = tRC (MIN))
SYM ICC1 ICC2
-7 4 2
-8 4 2
-12 4 2
UNITS NOTES mA mA
ICC3
85
75
65
70
mA
3, 4
ICC4
60
50
45
40
mA
3, 4
ICC5
85
75
65
70
mA
3
ICC6
85
75
65
70
mA
3, 5
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc. CAPACITANCE
PARAMETER Input Capacitance: A0-A10 Input Capacitance: RAS\, CAS\, WE\, OE\ Input/Output Capacitance: DQ SYM CI1 CI2 CIO MIN MAX 7 7 8 UNITS pF pF pF NOTES 2 2 2
MT4C4001J
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55C < TC < 125C; VCC = 5V 10%)
-7 PARAMETER Random READ or WRITE cycle time READ-WRITE cycle time FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS\ Access time from CAS\ Access time from column address Access time from CAS\ precharge RAS\ pulse width RAS\ pulse width (FAST PAGE MODE) RAS\ hold time RAS\ precharge time CAS\ pulse width CAS\ hold time CAS\ precharge time CAS\ precharge time (FAST PAGE MODE) RAS\ to CAS\ delay time CAS\ to RAS\ precharge time Row address setup time Row address hold time RAS\ to column address delay time Column address setup time Column address hold time Column address hold time (referenced to RAS\) Column address to RAS\ lead time Read command setup time Read command hold time (referenced to CAS\) Read command hold time (referenced to RAS\) CAS\ to output in Low-Z Output buffer turn-off delay WE\ command setup time SYM tRC tRWC tPC tPRWC tRAC tCAC tAA tCPA tRAS tRASP tRSH tRP tCAS tCSH tCPN tCP tRCD tCRP tASR tRAH tRAD tASC tCAH tAR tRAL tRCS tRCH tRRH tCLZ tOFF tWCS 70 70 20 50 20 70 10 10 20 5 0 10 15 0 15 50 35 0 0 0 0 0 0 20 35 50 10,000 MIN 130 180 40 90 70 20 35 35 10,000 100,000 80 80 20 60 20 80 10 10 20 5 0 10 15 0 15 60 40 0 0 0 0 0 0 20 40 60 10,000 MAX MIN 150 200 45 90 80 20 40 40 10,000 100,000 100 100 25 70 25 100 12 12 25 5 0 15 20 0 20 70 50 0 0 0 0 0 0 20 50 75 10,000 -8 MAX MIN 190 240 55 110 90 25 45 45 10,000 100,000 120 120 30 90 30 120 15 15 25 10 0 15 20 0 25 85 60 0 0 0 0 0 0 20 60 90 -10 MAX MIN 220 255 70 140 120 30 60 60 100,000 100,000 -12 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 20 21, 27 19 19 18 17 16 14 15 NOTES
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Austin Semiconductor, Inc.
MT4C4001J
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55C < TC < 125C; VCC = 5V 10%)
-7 PARAMETER Write command hold time Write command hold time (referenced to RAS\) Write command pulse width Write command to RAS\ lead time Write commend to CAS\ lead time Data-in setup time Data-in hold time Data-in hold time (referenced to RAS\) RAS\ to WE\ delay time Column address to WE\ delay time CAS\ to WE\ delay time Transition time (rise or fall) Refresh period (1,024 cycles) RAS\ to CAS\ precharge time CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH) CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH) WE\ hold time (CAS\-BEFORE-RAS\ REFRESH) WE\ setup time (CAS\-BEFORE-RAS\ REFRESH) WE\ hold time (WCBR test cycle) WE\ setup time (WCBR test cycle) OE\ setup prior to RAS during HIDDEN REFRESH cycle Output disable Output enable OE\ hold time from WE\ during READ-MODIFY-WRITE cycle SYM tWCH tWCR tWP tRWL tCWL tDS tDH tDHR tRWD tAWD tCWD tT tREF tRPC tCSR tCHR tWRH tWRP tWTH tWTS tORD tOD tOE tOEH 20 0 5 10 10 10 10 10 0 15 15 20 MIN 15 50 15 20 20 0 12 50 95 60 45 3 50 16 0 10 15 10 10 10 10 0 20 20 25 MAX MIN 15 60 15 20 20 0 15 60 105 65 45 3 50 16 0 10 20 10 10 10 10 0 25 25 25 -8 MAX MIN 20 70 20 25 25 0 18 70 130 80 55 3 50 16 0 10 25 10 10 10 10 0 25 25 -10 MAX MIN 25 80 25 30 30 0 25 90 140 90 60 3 50 16 -12 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns 27 23 26 5 5 25, 28 25, 28 25, 28 25, 28 21 21 21 22 22 NOTES
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc.
NOTES:
1. All voltages referenced to Vss. 2. This parameter is sampled, not 100% tested. Capacitance is measured with Vcc=5V, f=1 MHz at less than 50mVrms, TA = 25C 3C, Vbias = 2.4V applied to each input and output individually with remaining inputs and outputs open. 3. Icc is dependent on cycle rates. 4. Icc is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the output open. 5. Enables on-chip refresh and address counters. 6. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-55C < TA < 125C) is assured. 7. An initial pause of 100s is required after power-up followed by eight RAS\ refresh cycles (RAS\-ONLY or CBR with WE\ HIGH) before proper device operation is assured. The eight RAS\ cycle wake-up should be repeated any time the 16ms refresh requirement is exceeded. 8. AC characteristics assume tT = 5ns. 9. V IH (MIN) and V IL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 10. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 11. If CAS\ = VIH, data outputs (DQs) are High-Z. 12. If CAS\ = VIL, data outputs (DQs) may contain data from the last valid READ cycle. 13. Measured with a load equivalent to two TTL gates and 100pF. 14. Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 15. Assumes that tRCD > tRCD (MAX) 16. If CAS\ is LOW at the falling edge of RAS\, DQs will be maintained from the previous cycle. To initiate a new cycle and clear the data out buffer, CAS\ must be pulsed HIGH for tCPN. 17. Operation within the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, then access time is controlled exclusively by tCAC. 18. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, then access time is controlled exclusively by tAA. 19. Either tRCH or tRRH must be satisfied for a READ cycle. 20. tOFF (MAX) defines the time at which the output achieves the open circuit conditions and is not referenced to VOH or VOL. 21. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY-WRITE cycles. tRWD, tAWD, and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY-WRITE cycles and the data output will remain an open circuit throughout the entire cycle. If tRWD > tRWD (MIN), tAWD > tAWD (MIN) and tCWD > tCWD (MIN), the cycle is a READ-MODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of the data out is indeterminate. OE\ held HIGH and WE\ taken LOW after CAS\ goes LOW results in a LATE-WRITE (OE\ controlled) cycle. t WCS, t RWD , t CWD , and t AWD are not applicable in a LATE-WRITE cycle. 22. These parameters are referenced to CAS\ leading edge in EARLY-WRITE cycle and WE\ leading edge in LATE-WRITE cycles and WE\ leading edge in LATE-WRITE or READ-MODIFY-WRITE cycle. 23. If OE\ is tied permanently LOW, LATE-WRITE or READ-MODIFY-WRITE operations are not possible. 24. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE\=LOW and OE\=HIGH. 25. tWTS and tWTH are setup and hold specifications for the WE\ pin being held LOW to enable the JEDEC test mode (with CBR timing constraints). These two parameters are the inverts of tWRP and tWRH in the CBR REFRESH cycle. 26. LATE-WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE\ HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS\ remains LOW and OE\ is taken back LOW after tOEH is met. If CAS\ goes HIGH prior to OE\ going back LOW, the DQs will remain open. 27. The DQs open during READ cycles once tOD or tOFF occur. If CAS\ goes HIGH first, OE\ becomes a "don't care." If OE\ goes HIGH and CAS\ stays LOW, OE\ is not a "don't care;" and the DQs will provide the previously read data if OE\ is taken back LOW (while CAS\ remains LOW). 28. JEDEC test mode only.
MT4C4001J
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc.
READ CYCLE
MT4C4001J
EARLY-WRITE CYCLE
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc.
MT4C4001J
READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES)
FAST-PAGE-MODE READ CYCLE
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc.
FAST-PAGE-MODE EARLY-WRITE CYCLE
MT4C4001J
FAST-PAGE-MODE READ-WRITE CYCLE (LATE-WRITE and READ-MODIFY-WRITE CYCLES)
*tPC = LATE-WRITE cycle tPRWC = FAST READ-MODIFY-WRITE cycle
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Austin Semiconductor, Inc.
RAS\-ONLY REFRESH CYCLE (ADDR = A0-A9; WE\ = Don't Care)
MT4C4001J
CAS\-BEFORE-RAS\ REFRESH CYCLE (A0-A9, and OE\ = DON'T CARE)
HIDDEN REFRESH CYCLE24 (WE\ = HIGH, OE\ = LOW)
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc.
4 MEG POWER-UP AND REFRESH CONSTRAINTS
The EIA/JEDEC 4 Meg DRAM introduces two potential incompatibilities compared to the previous generation 1 Meg DRAM. The incompatibilities involve refresh and power-up. Understanding these incompatibilities and providing for them will offer the designer and system user greater compatibility between the 1 Meg and 4 Meg.
MT4C4001J
POWER-UP
The 4 Meg JEDEC test mode constraint may introduce another problem. The 1 Meg POWER-UP cycle requires a 100s delay followed by any eight RAS\ cycles. The 4 Meg POWER-UP is more restrictive in that eight RAS\-ONLY or CBR REFRESH (WE\ held HIGH) cycles must be used. The restriction is needed since the 4 Meg may power-up in the JEDEC specified test mode and must exit out of the test mode. The only way to exit the 4 Meg JEDEC test mode is with either a RAS\-ONLY or a CBR REFRESH cycle (WE\ held HIGH).
REFRESH
The most commonly used refresh mode of the 1 Meg is the CBR (CAS\-BEFORE-RAS\) REFRESH cycle. The CBR for the 1 Meg specifies the WE\ pin as a "don't care." The 4 Meg, on the other hand, specifies the CBR REFRESH mode with the WE\ pin held at a voltage HIGH level. A CBR cycle with WE\ LOW will put the 4 Meg into the JEDEC specified test mode (WCBR).
SUMMARY
1. The 1 Meg CBR REFRESH allows the WE\ pin to be "don't care" while the 4 Meg CBR requires WE\ to be HIGH. 2. The eight RAS\ wake-up cycles on the 1 Meg may be any valid RAS\ cycle while the 4 Meg may only use RAS\-ONLY or CBR REFRESH cycles (WE\ held HIGH).
COMPARISON OF 4 MEG TEST MODE AND WCBR TO 1 MEG CBR
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #103 (Package Designator CN) SMD 5962-90847, Case Outline R
MT4C4001J
D A
Q
E S1
Pin 1
L
b2
e
b
R
eA c
SMD Specifications SYMBOL A b b2 c D E eA e Q L S1 R MIN --0.014 0.045 0.008 --0.220 0.300 BSC 0.100 BSC 0.015 0.125 0.005 90 0.070 0.200 --105 MAX 0.200 0.026 0.065 0.018 1.060 0.310
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
* All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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DRAM
Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #104 (Package Designator C) SMD 5962-90847, Case Outline U
MT4C4001J
D D1 A
Q L
E S1
Pin 1
b2
e
b
eA c
SMD Specifications SYMBOL A b b2 c D D1 E eA e Q L S1 MIN --0.015 0.045 0.008 0.980 0.890 0.380 0.385 0.100 BSC 0.015 0.125 --0.060 0.200 0.070 MAX 0.175 0.021 0.065 0.014 1.030 0.910 0.410 0.420
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
* All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc. MECHANICAL DEFINITIONS* ASI Case #400 (Package Designator CZ) SMD 5962-90847, Case Outline N
MT4C4001J
SMD SPECIFICATIONS SYMBOL MIN MAX A 0.355 0.405 b 0.016 0.023 b2 0.035 0.045 c 0.008 0.015 e 0.045 0.055 eA 0.085 0.115 D 1.035 1.065 E 0.100 0.130 L 0.125 0.200 L1 0.015 0.050 NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
* All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc.
MT4C4001J
ASI Case #202 (Package Designator ECN) SMD 5962-90847, Case Outline T
L1 S
e
E
E1
b R
L D
A A1
SYMBOL A A1 b D E E1 e L L1 R S
SMD SPECIFICATIONS MIN MAX 0.060 0.080 0.035 TYP 0.022 0.028 0.343 0.357 0.665 0.685 0.590 0.610 0.050 TYP 0.045 0.055 0.080 0.100 0.006 0.010 0.025 0.050
NOTE: These dimensions are per the SMD. ASI's package dimensional limits may differ, but they will be within the SMD limits.
* All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc. MECHANICAL DEFINITION*
ASI Case #504 (Package Designator ECJ)
MT4C4001J
A
b2
b1
e
L D D1 E1
b
A1 E
SYMBOL A A1 b b1 b2 D D1 E E1 e L
ASI SPECIFICATIONS MIN MAX 0.120 0.140 0.066 0.078 0.022 0.028 0.050 TYP 0.090 0.11 0.665 0.685 0.592 0.608 0.345 0.355 0.345 0.360 0.045 0.055 0.057 0.063
*All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc. MECHANICAL DEFINITION*
ASI Case #600 (Package Designator ECG)
MT4C4001J
SYMBOL A A1 b b1 b2 D D1 E E1 E2 e e1 L
ASI PACKAGE SPECIFICATIONS MIN MAX 0.120 0.140 0.066 0.078 0.022 0.028 0.050 TYP 0.090 0.110 0.665 0.685 0.592 0.608 0.345 0.355 0.482 0.498 0.442 0.458 0.045 0.055 0.014 Dia. TYP 0.057 0.063
*All measurements are in inches.
MT4C4001J Rev. 1.5 10/02
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Austin Semiconductor, Inc.
MT4C4001J
ORDERING INFORMATION
EXAMPLE: MT4C4001JCN-8/883C Device Package Speed ns Number Type MT4C4001J CN -7 MT4C4001J CN -8 MT4C4001J CN -10 MT4C4001J CN -12 EXAMPLE: MT4C4001JCZ-7/883C Device Package Speed ns Number Type MT4C4001J CZ -7 MT4C4001J CZ -8 MT4C4001J CZ -10 MT4C4001J CZ -12 EXAMPLE: MT4C4001JECJ-7/IT Device Package Speed ns Number Type MT4C4001J ECJ -7 MT4C4001J ECJ -8 MT4C4001J ECJ -10 MT4C4001J ECJ -12 EXAMPLE: MT4C4001JC-12/883C Device Package Speed ns Number Type MT4C4001J C -7 MT4C4001J C -8 MT4C4001J C -10 MT4C4001J C -12 EXAMPLE: MT4C4001JECN-10/XT Device Package Speed ns Number Type MT4C4001J ECN -7 MT4C4001J ECN -8 MT4C4001J ECN -10 MT4C4001J ECN -12 EXAMPLE: MT4C4001JECG-12/IT Device Package Speed ns Number Type MT4C4001J ECG -7 MT4C4001J ECG -8 MT4C4001J ECG -10 MT4C4001J ECG -12
Process /* /* /* /*
Process /* /* /* /*
Process /* /* /* /*
Process /* /* /* /*
Process /* /* /* /*
Process /* /* /* /*
*AVAILABLE PROCESSES IT = Industrial Temperature Range XT = Extended Temperature Range 883C = Full Military Processing
-40oC to +85oC -55oC to +125oC -55oC to +125oC
MT4C4001J Rev. 1.5 10/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
19
DRAM
Austin Semiconductor, Inc.
MT4C4001J
ASI TO DSCC PART NUMBER CROSS REFERENCE*
ASI Package Designator CZ
ASI Part # MT4C4001JCZ-8/883C MT4C4001JCZ-10/883C MT4C4001JCZ-12/883C SMD Part # 5962-9084703MNA 5962-9084702MNA 5962-9084701MNA
ASI Package Designator C
ASI Part # MT4C4001JC-8/883C MT4C4001JC-10/883C MT4C4001JC-12/883C SMD Part # 5962-9084703MUA 5962-9084702MUA 5962-9084701MUA
ASI Package Designator CN
ASI Part # MT4C4001JCN-8/883C MT4C4001JCN-10/883C MT4C4001JCN-12/883C SMD Part # 5962-9084703MRA 5962-9084702MRA 5962-9084701MRA
ASI Package Designator ECN
ASI Part # MT4C4001JECN-8/883C MT4C4001JECN-10/883C MT4C4001JECN-12/883C SMD Part # 5962-9084703MTA 5962-9084702MTA 5962-9084701MTA
* ASI part number is for reference only. Orders received referencing the SMD part number will be processed per the SMD.
MT4C4001J Rev. 1.5 10/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20

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